useful links
the spec sheet of the OAA160 optocmos switch is at the manufacturer's site
Notes
..from a while ago
Assume for now that we have 8 channels, each channel has a length and a pointer that says where in the array it is (bit too). parameters: base pointer (16 bits) 16bit pointer to the sample, which allows 3 bits per byte, 13bits for address - more than we need. length (16 bits too) ~ why not
2. Then every stimuli is biphasic, ie output high-impedance, a high, b low, b high, a low, highimp. Emerson has it covered in the output, though I'll leave space for both channels in memory. 3. need to have a stimuli where there is a simple tetanic series, followed by a delay, endlessly repeating. to do this, we should write a simple program per channel that converts 4 parameters to a behavior. the program gets a count in a named variable. the parameters (for now): total period, length of tetanus, tetanus period, length of pulse. the program would develop the biphasic response programatically, too. -16 channels of stimulation, port B and D. -we have 1536 bytes of ram, so if we give each channel 32 bytes of parameters, we use 512 bytes - only a third of mem. can put other stuff elsewhere, one block for port B (BSR = 0001), one for port D (BSR = 0010). organization within the 32 bytes: 0 - config. bit 0: enabled. (skip the channel if it is not enabled... the serial control that enables it must reset the counter. bit 1: the positive output bit 2: repeat bit 3: the negative output. bit 4-7: the algorithm. 1, 2, 3 - the counter, time parameter. (1 is LSByte) 4, 5, 6 - the limit. (24 bits - 16.7e6 * 1e-4 (resolution) = 16700 seconds, 4.6 hours (plenty of time!) 31 - more config. bit 0-2: the priority encoding that enables the channel. (3 bits, allows you to select one per channel or trigger many channels from one).
7 - 30 - whatever the algorithm wants/needs.
alg1: the pulser. 7: present state (1 = pulse, 2 = off, 4 = biphasic oputput, 0 = stop) 8-9: count 10-11: pulse length, in samples 12-13: off length, in samples 14, 15, 16: stop pulsing at this count 17, 18: biphasic counter.
alg2: programmable sequence idea: every 'spike' is represented as a 16-bit integer. this allows 6.5 seconds between spikes, which is enough as far as I can imagine. 7: present state 1 -> exclude the first spike (config) 2 -> disable output flag (internal) 8-9: count. the counter increments until it is equal to the value stored at the pointer, whence the pointer is incremented 2, and a new limit is loaded. you have to write a zero to the counter before enabling the channel. 10-11: pointer (to flash) 12-13: base pointer 14-15: end pointer (the pulse pointed to by this location is not produced) 16-17: pulse length 18-19: biphasic length
SERIAL: two state control registers serialstate: bit 0: write the next char to SERADDR bit 1: write the next char to location pointed by address bit 2: read from address sent. bit 3: write to base addr LSB bit 4: write to base addr MSB bit 5: write to RAM flash buffer bit 6: read from flash state bit 7: misc commands ie 0x00 - disable outputs 0x01 - enable outputs serialreadf: bit 0: put the next recieved byte into LSB of tableaddress bit 1: put the next byte into MSB tableaddress, reply with data need to figure out some way of writing whatever we want to any address, while still employing simple command codes. it could to rely on feedback, or the present enable/disable scheme that seems to work alright. so: writing to program memory. first you send 0xfd while not writing a value - should get back a 'F' for flash. then send the base address, where the lowest 6 bits are zero, LSB then MSB - then send 64 bytes of data, with ack on each one, except the last - after the last byte, the PIC erases and then programs flash memory with the sent data; when it is done it acks with a 'D' (or something) and returns to the wait state.
modification to allow inclusion/exclusion of first spike in the arbitrary pattern generator:
1. when the channel is triggered, the counter is loaded with an initializer that bypasses _both_ the pulse and byphasic outputs (i.e. it is init with the biphasic - for the increment occurs before the comparison, so bnn will always fail.) to accomodate this counter initialization, when writing to flash the first period will be desired delay to first spike + biphasic period.
2 . the most elegant way would be to incorporate something into the algorithm - an extra bit - that when the table pointer = base pointer and counter = 0 and ignore first pulse =1 it sets a bit to clear the output. this is cleared when the pointer is incremented next/ counter is zeroed next.
alt: uh, but wait! what if the first program memory entry is 0? what will the behaviour be? it will immediatly increment the table pointer and clear the counter - so it will put out a spike, doh. won't work.
Emerson's new current-controlled stimulator
hand drawn schematic the fax degraded the quality, but still very useful, as it includes part numbers, voltages, and values.
